1. Field of the Invention
The present invention relates to special purpose circuitry for performing computer graphics computations. More specifically, the present invention relates to an architecture for a graphics controller embedded within a core logic unit of a computer system.
2. Related Art
The increasing power of computational circuitry has recently been applied to computer graphics applications, which manipulate graphical information for representing images on a computer system display. Computer graphics applications involve large volumes of data, which must be typically transformed through computationally-intensive numerical operations. In order to improve performance on these computer graphics applications, computer systems typically contain a dedicated piece of circuitry known as a xe2x80x9cgraphics controllerxe2x80x9d to perform computer graphics operations. This allows a computer system to off-load computationally-intensive graphics operations, such as 2-dimensional and 3-dimensional processing, from the central processing unit of the computer system onto the graphics controller. In spite of the improved performance provided by graphics controllers, the increasing computational requirements of computer graphics applications continue to push the capabilities of present computer system architectures.
This increasing demand for performance on computer graphics applications has been matched with corresponding performance increases in certain computer system components. (1) Graphics controllers are becoming increasingly more powerful as increasing integration densities allow faster and more sophisticated graphics processing circuitry to be incorporated onto a graphics controller chip. (2) Recent developments in memory system designs have greatly increased memory bandwidth. New memory architectures, such as Rambus and SyncLink, incorporate a synchronous clocked interface into each memory chip, thereby allowing data from within a page of memory to be clocked out of a memory chip in a continuous high-speed stream.
However, these increases in processing power and memory bandwidth have not been matched by a corresponding increase in a computer system""s ability to move data between computer system components. For example, data transfers between processor and graphics controller, and between graphics controller and system memory are presently constrained by the bandwidth of the busses and/or data channels that couple these system components together.
To alleviate this problem, the Intel Corporation of Sunnyvale, Calif. has recently developed the Accelerated Graphics Port (AGP) architecture to handle communications between a graphics controller and the rest of the computer system. The AGP standard specifies a 32-bit, 133 MHz bus between the graphics controller and the computer system. An AGP bus can be used in a number of ways. For example, if texture map data for a graphics application cannot fit into a local frame buffer attached the graphics controller, the texture map data can instead be stored in system memory, where it can be accessed by the graphics controller through the AGP. Unfortunately, as the processing power of graphics controllers continues to increase, and as system memory bandwidth continues to increase, communication channels, such as AGP, are becoming a bottleneck to performance in computer graphics applications.
What is needed is a computer system architecture that facilitates high-bandwidth data transfers between a graphics controller and other computer systems components.
The present invention provides an architecture for a core logic unit including an embedded graphics controller. This architecture facilitates high-bandwidth communications between the graphics controller and other computer system components, such as the processor and the system memory. Thus, one embodiment of the present invention provides a core logic unit within a computer system including a processor interface for communicating with a processor, a memory interface for communicating with a system memory, and a bus interface for communicating across a computer system bus. It also includes a switch, coupled to the processor interface, the memory interface and the bus interface, for facilitating data transfers between these interfaces. The switch is connected to a graphics controller, which is located on the same semiconductor chip as the switch, for performing computations for displaying images on a computer system display. A variation of the above embodiment includes a Graphics Address Relocation Table (GART), which performs address translations on-the-fly for addresses crossing the switch that fall within the reserved range of addresses, and does not perform translations for other addresses. These address translations map addresses from the reserved range of graphics addresses to locations in system memory which contain graphics data. In another variation, the graphics controller is coupled to the switch through both a processor port, for communicating with a processor, and a separate memory port, for communicating with the system memory. The processor port and the memory port are each connected to the switch through separate read and write paths.